Design & Analysis of Modified Conditional Data Mapping Flip-Flop to Ultra Low Power and High Speed Applications

In the history, the major issues of the VLSI designer were area, cost, performance, and reliability; power concern was typically of only lesser importance. But more than the last few years’ power in the circuit is the major difficulty at the present days which is being faced by the very large scale integration industries. The power dissipation in several circuits is typically take place by the clocking system which includes the clock distribution system and sequential elements (flip flops and latches) in it. The quantity of power dissipation by any clock distribution system and sequential circuit in any chip is as regards of 30% to 60% of the overall chip power dissipation by the circuit. Clock is the most vital signal present in the chip. Clock signals are synchronizing signals which offer timing references for computation of in the least work in synchronous digital systems. In this paper the power of the sequential circuit is reduced which in position reduce the on the whole power of the chip. Here dissimilar low power techniques for the lowering static power dissipation are second-hand in the sequential circuit are surveyed. The work analyses the power consumption and propagation delay of flipflop designs. In Tanner 14.0μm CMOS technology designs are implemented. Keyword: Flip-flop, Low power, CMOS Circuit, delay optimization.